Praveen Kumar
Assistant Regional Director
IGNOU Regional Centre, Pune
Email: binu_praveen@yahoo.com
Mobile: +91 94220 31727
Telephone: +91 20 25671867 (O), 25651187 (R)
Current Address:
D-2/306 MSFC Quarters
Senapati Bapat Road
Pune, Maharashtra
India – 411 016
Phone # +91 20 25561187
Permanent Address:
C/O Dr Rajendra Gautam
B-226, Gali#6, Rajnagar-I
Palam Colony, New Delhi
India – 110 077
Phone # +91 11 25362321
Educational Qualifications:
M Tech, Electrical Engineering
Indian Institute of Technology Bombay, India
Specialization: Microelectronics
Marks: 8.89 (On 10-point scale)
Year: 2000 - 2002
Courses: VLSI Design, System Hardware Design, Modern Electronic Design Techniques, Computer-Aided Analysis and Design, Hardware Description Language, Digital Signal Processing, Physical Electronics, Physics of Transistor, VLSI Technology, and Microelectronics Lab.
Masters of Science, Physics
Indian Institute of Technology Delhi, India
Marks: 8.80 (On 10-point scale)
Year: 1998 – 2000
Courses: Solid State Physics, Semiconductor Physics, Analog Electronics, Advance Electronics (Digital), Microelectronics, Opto-electronics, and Physics of Thin Films.
Bachelor of Science, Physics (H)
University of Delhi, India
Marks: 74.5 %
Year: 1995 - 1998
Projects:
Jitter Analysis and Modeling of PLL (M Tech):
Starting with a given specification, we first designed a CMOS PLL at transistor level. We then identified various sources of noise at different stages (Phase Detection, Charge Pump, Filter and Voltage Controlled Oscillator) of PLL, and demonstrated how noise from various sources manifest as jitter at the output of PLL.
For this work we used mixed signal simulator SABER, general purpose circuit simulator SPICE, and well known software for mathematical tools and techniques MATLAB. MATLAB was basically used to obtain Fast Fourier Transformation (FFT) of raw data obtained from SPICE/SABER for frequency domain analysis.
This work provided useful insight into how jitter/phase noise in CMOS PLL, one of the building blocks of RF Communication Circuits, can be minimized.
Bulk & Surface Passivation and Antireflection Coating of Silicon (M Sc):
Multi-crystalline solar cells have poor efficiency (conversion of light energy into electrical energy) due to large reflection losses and also due to excessive recombination losses. In this work, we used thin layer of silicon nitride as an anti-reflection coating in order to minimize the reflection losses, and then used passivation technique, annealing the sample Hydrogen environment for saturating the dangling bonds, in order to minimize the recombination losses.
For observation and analysis in this work, we used FT-IR (Fourier Transform Infrared Spectroscopy), Ellipsometer and Photo-spectrometer.
Best-fit-curve for an experimental data-set for given goodness of fit (B Sc):
Many scientific and research works require obtaining a best fit curve for the given experimental data. We therefore used "Gram-Schmidt Orthogonalization Technique" to obtain best-fit polynomial with appropriate goodness of fit (chi-square Distribution) for the given data-set. We used PASCAL programming language to generate the coefficients of the polynomial.
Course Projects during M Tech (Microelectronics):
Under M Tech programme, various course projects were also completed in order to fulfill the requirements of different courses. Among other things, those projects are - implementation of ALU (16 bit) and Interrupt Controller Unit of 80186 using Verilog; design of single slope ADC, Triangular-Wave generator, Square-Wave generator, two stage OPAMP, Band-gap Voltage Reference using SPICE; implementation of ‘IEEE GPIB Source and Acceptor Handshake’ and ‘MOV instruction of 8085’ using IRSIM, circuit-layout of ‘MOV instruction of 8085’ (one designed earlier using IRSIM) in MAGIC; implementation of BFS, DFS, and MST using C++ programming language; design of complete CMOS process for 70-nm technology using SUPREM-IV; design of NMOS for 250-nm technology (in T-SUPREM) and study of Id-Vd, Id-Vg, VT roll-off and sub-threshold swing with respect to different channel implant depth was done using MIDICI.
Professional Experiences:
After completion of my masters from IIT Bombay in 2002, due to deep interest in academics, I began my career with teaching and research by associating myself with private academic institutions. Initially, I taught college level students preparing for various competitive examination and also higher secondary level students preparing for engineering entrance examinations. Research activities mainly focused on deepening my understanding of emerging issues in the area of RF Circuit Design. Later, in 2005, I entered into formal professional academic life by joining Galgotia’s College of Engineering and Technology (GCET), Greater Noida, affiliated to Uttar Pradesh Technical University (UPTU), Lucknow, as faculty in Electronics Department.
Galgotia’s College of Engineering and Technology (GCET), Greater Noida, Uttar Pradesh (July – December 2005):
Here, I taught VLS: 913 (HDL based FPGA Design) to first semester Sequential M Tech students, Solid State Devices and Circuits (EC 301) to third semester and Analog Integrated Circuits (EC 502) to fifth semester B Tech students. Besides, I took Analog Electronics lab for these students.
Birla Institute of Science and Technology (BITS), Pilani, Rajasthan (December 2005 – May 2006):
Here, I was instructor for the two courses: Analog and Digital VLSI Design (EEE C 443) and Analog Electronics (EEE/INSTR C 364) for sixth semester students. I also took Analog Electronics lab for these students. Besides, I guided two students in their course project - one master level student of Microelectronics specialization in Design of different OP-AMPs for various specifications under Professional Practice (BITS G 620) course; and another bachelor degree student in Design of Advance Encryption Standard, AES – 128, Module for Zigbee Architecture for Computer Projects (BITS C 331/ BITS C 335) course.
Indira Gandhi National Open University (IGNOU), New Delhi (May 2006 - Present):
I joined IGNOU as Assistant Regional Director. Regional Centre Bhopal was my first place of posting. Later in July 2008, I was transferred to Regional Centre Pune.
At IGNOU, the nature of work being more of academic-administration, I dealt with, among other things, Admissions, Establishment of Learner Support Centres, Counsellings, Examinations, Legal Issues, Orientation Programmes, Workshops, Convocation and Publicity related issues.
Admissions related activities were mainly handled in Regional Centre Bhopal which catered to 37, out of 48 districts of Madhya Pradesh. There used to be about 6000-7000 student intake each year. Here I ensured proactive supports services (academic and otherwise) to all the learners of IGNOU at all the stages - from pre-admission guidance to award of final degree etc. We also organized Spot Counsellings for B Ed admissions, admitting about 800 students in 2/3 days. Selling admission form, scrutinizing admission applications, preparing merit-list (whenever necessary), issuing confirmation letter and identity card, organizing induction meetings etc were major activities I performed as an admission incharge.
I also played a key role in managing EDUSAT terminals, eight places in different parts of Madhya Pradesh, so as to ensure effective participation of IGNOU learners and others in the teleconferencing/ videoconferencing programmes. Besides, I also managed IT (Information Technology) infrastructure of entire Bhopal Regional Centre Office, including its Computer Laboratory.
I was also vested with the responsibilities of the part-time Coordinator at Regional Centre Bhopal for Computer related programmes MCA/BCA/CIC/PGDLAN etc, and two other short term programmes ACPDM and ACE. As a coordinator I arranged academic-counsellings for those learners. Besides, I also took counsellings for MCA (MCS-12 & MCSE-4) and CIC learners.
I also dealt with student-related legal cases at Regional Centre Bhopal. In this regard, I used to prepare suitable response for the legal notices, used to coordinate with the lawyer in handling the cases, and visit District Consumer Dispute Redressal Forum with our lawyer to represent IGNOU. Verdict of District Consumer Forum, Guna, Madhya Pradesh, dated 17th December 2007, one such cases under us, was in favour of IGNOU.
Together with Regional Director, at Regional Centre Bhopal, I also participated in promotion and publicity of IGNOU programmes through Interactive Radio Counsellings at All India Radio/Gyanwani and Press Conference etc.
At Regional Centre Pune, I have been dealing with establishment of new Learner Support Centres (LSCs) for different programmes of IGNOU in various academic and other institutions. I am in fact first point of contact for people/ institutions, under the jurisdiction of Regional Centre Pune, seeking to collaborate with IGNOU under various schemes. So far, we got seven such Centres established in different Colleges, NGOs and Hospitals located in various districts of Maharashtra. I also played key role in handling proposals for establishment of about 6 other Centres. Besides, some more proposals in this regard are under process, almost at final stage of notification. In addition, I have been dealing with monitoring of academic support services to learners at various LSCs, appointment of part time staffs at those LSCs, and empanelment of academic counsellors/evaluators etc. So far I got more than 300 academic counsellors empanelled and about 50 evaluators approved for different courses of IGNOU. Besides, I got several new programmes of IGNOU activated in various existing LSCs under Regional Centre Pune.
For examination duties, surprise as well as otherwise, I have visited various examination centres Of IGNOU under Bhopal Regional Centre, and also those under Pune Regional Centre, as an Observer for entrance/term-end examinations. Besides, I also worked as Centre Superintendent (thrice – July 2006, January 2007 and July 2007) for conducting term-end practical examinations for MCA/BCA/CIC/PGDLAN learners at Regional Centre Bhopal. I also coordinated those examinations at two other places in Madhya Pradesh – Indore and Gwalior. In addition I also organized project-evaluation cum workshop for ACE learners at Bhopal Regional Centre (on 12th November 2006, 29th April 2007 and 16th December 2007).
Organizing induction meetings, orientation programmes, workshop etc has also been part of my responsibilities. I organized 2-days orientation programmes for Academic Counsellors of Auxiliary Nurse Midwifery /Female Health Workers (ANM/FHW) [13-14th July 2006, at Regional Centre Bhopal], 10-days extended-contact-programme (ECP) for the students of Post Graduate Diploma in Higher Education (PGDHE) [17-26th May 2007, at Regional Centre Bhopal]; 2-days orientation programme for LSC functionaries [20-21st February 2010, at Regional Centre Pune]; and several induction meetings for IGNOU learners at the commencement of new batch at Regional Centre Bhopal. Besides, I also played major role in organizing IGNOU Convocations at Regional Centre Office and I compered this event twice.
Conferences/Workshops /Short Courses Attended:
10th International Workshop on Semiconductor Devices, 14-18 December 1999, IIT Delhi, New Delhi, India.
VLSI System, Design and Technology (VSDT) 2000, 9-11 January 2001, IIT Bombay, Mumbai, India.
National Workshop on VLSI Design and Embedded Systems, 24-26 February 2006, BITS Pilani, Rajasthan, India.
Design for Testability: Theory and Practice (short course on VLSI Testing by Dr C P Ravikumar, Texas Instruments, Bangalore), 27th February – 3rd March 2006, BITS Pilani, Rajasthan, India.
Short course on ADC by Mr. Prakash, Cosmic Circuits, Bangalore, 27-29 March 2006, BITS Pilani, Rajasthan, India.
Intensive Teaching Workshop (ITW), 1st February – 26th April 2006, BITS Pilani, Rajasthan, India.
Induction-cum-Orientation Programme for Newly joined Academics at the Regional Centres, 6 – 10th November 2006, Indira Gandhi National Open University (IGNOU), New Delhi, India
International Conference on Issues in Public Policy and Sustainable Development (presented a paper on “Global Dimming”), 26 – 28 March 2008, Indira Gandhi National Open University (IGNOU), New Delhi, India
National Workshop on Research in Distance and Online Learning, 23 – 27 November 2009, Indira Gandhi National Open University (IGNOU), New Delhi, India
Accelerating Commercialisation of Technology and InnoVation -Tech Transfer (ACTIV-TT) Workshop, 27-28 September 2010, Venture Centre & Accelerator India, NCL Innovation Park, Pune, Maharashtra, India
Talk/Lecture Delivered:
A General talk on “VLSI Design Methodology” at Chip-Focus, Seminar on VLSI Design and Embedded System, 15th September 2006, Oriental Institute of Science and Technology (OIST), Bhopal, Madhya Pradesh [About 200 students from OIST and other neighbouring engineering colleges participated in the programme]
A talk on “ASIC Design Methodology” at Sensitization session on VLSI, Bhopal Chapter of Computer Society of India & MP State Centre of the Institution of Engineers, 8th October 2006, Bhopal, Madhya Pradesh [About 30 people mainly faculties of various engineering college participated in the event]
A brief talk on “Effective Utilization of EDUSAT and Teleconferencing facility: Concrete Suggestions” during the Orientation Programme, 6-10th November 2006, conducted by Indira Gandhi National Open University (IGNOU), New Delhi [About 25 people, all IGNOU academics and faculties, were present in the seminar]
A lecture on “CMOS Fabrication Process Flow” at Chip Focus – a National Seminar on VLSI Design and Embedded System, 30-31st March 2007, organized jointly by the IETE, CSI and OIST, Bhopal [About 500 students, all bachelor degree students from OIST and other neighbouring engineering colleges, attended the lecture]
A talk on “UGC and its Role in Present Century”, at the Extended Contact Programme for Post Graduate Diploma in Higher Education (PGDHE), 17-26th May 2007, IGNOU Regional Centre, Bhopal [6 PGDHE students of IGNOU participated in the event]
A talk on “Scheduling and Monitoring of Counselling (Theory & Practical) in ODL System” at Orientation Programme for LSC functionaries, 20-21st February 2010, IGNOU Regional Centre, Pune [about 20 participants attended the talk]
A talk on “Joy of Science” at Indian Institute of Aeronautical Engineering and Information Technology, Pune, on 20th March 2010 [About 100 students of the college were present in the talk]
Achievements:
• R. S. Narayanan Scholarship (1998-1999)
• Prof. Vidya Bhusan Scholarship (1999-2000)
• Prof. Neeraj Srivastava Award (2000)
• GATE 2000: 98.92 percentiles with an all India rank of 14.
• Qualified in national level Junior Research Fellowship (JRF)/Lecturership
Eligibility Test (NET) in Physics conducted by CSIR-UGC, India in the year
2000.
• Fellow of Tata Consultancy Services at IIT Bombay, July 2000-Jan. 2002
